System Settings

 
Environment Settings
Environment Variable xst ngdbuild
LD_LIBRARY_PATH /mnt/hdd/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/common/lib/lin64
< data not available >
LMC_HOME /mnt/hdd/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64 < data not available >
PATH /mnt/hdd/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/mnt/hdd/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/mnt/hdd/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games
< data not available >
XILINX /mnt/hdd/Xilinx/14.7/ISE_DS/ISE/ < data not available >
XILINX_DSP /mnt/hdd/Xilinx/14.7/ISE_DS/ISE < data not available >
XILINX_EDK /mnt/hdd/Xilinx/14.7/ISE_DS/EDK < data not available >
XILINX_PLANAHEAD /mnt/hdd/Xilinx/14.7/ISE_DS/PlanAhead < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   wall.prj  
-ifmt   mixed MIXED
-ofn   wall  
-ofmt   NGC NGC
-p   xc9500xl  
-top   wall  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy Yes YES
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-bus_delimiter Bus Delimiter <> <>
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-resource_sharing   YES YES
-iobuf   YES YES
-equivalent_register_removal   YES YES
 
Operating System Information
Operating System Information xst ngdbuild
CPU Architecture/Speed Intel(R) Core(TM) i7-4720HQ CPU @ 2.60GHz/3389.242 MHz <  data not available  >
Host mike-laptop <  data not available  >
OS Name Ubuntu <  data not available  >
OS Release Ubuntu 14.04.3 LTS <  data not available  >