Random Project Status (08/31/2015 - 13:49:38)
Project File: Random.xise Parser Errors: No Errors
Module Name: Random Implementation State: Fitted
Target Device: xc9572xl-5VQ44
  • Errors:
No Errors
Product Version:ISE 14.3
  • Warnings:
2 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Aug 31 13:49:18 201502 Warnings (2 new)3 Infos (3 new)
Translation ReportCurrentMon Aug 31 13:49:25 2015000
CPLD Fitter Report (Text)CurrentMon Aug 31 13:49:28 201501 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon Aug 31 13:48:59 2015
Post-Fit Simulation Model Report  

Date Generated: 08/31/2015 - 13:49:38