obstacle Project Status | |||
Project File: | Obstacle.xise | Parser Errors: | No Errors |
Module Name: | obstacle | Implementation State: | Fitted |
Target Device: | xc9572xl-5VQ44 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Aug 31 16:45:07 2015 | 0 | 0 | 0 | |
Translation Report | Current | Mon Aug 31 16:45:13 2015 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | Mon Aug 31 16:45:16 2015 | 0 | 1 Warning (1 new) | 0 | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Wed Aug 26 13:59:45 2015 | |
Post-Fit Simulation Model Report |