Loop Project Status (08/31/2015 - 11:51:41)
Project File:	Looping.xise	Parser Errors:	No Errors
Module Name:	Loop_IFL	Implementation State:	Fitted
Target Device:	xc9572xl-5VQ44	Errors:
Product Version:	ISE 14.3	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
Post-Fit Simulation Model Report

Date Generated: 08/31/2015 - 11:51:41