top Project Status | |||
Project File: | Light.xise | Parser Errors: | No Errors |
Module Name: | top | Implementation State: | New |
Target Device: | xc9572xl-5VQ44 |
|
|
Product Version: | ISE 14.7 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Tue Sep 29 14:05:41 2015 | |
Post-Fit Simulation Model Report |