logic Project Status
Project File: OwlPress.xise Parser Errors: No Errors
Module Name: logic Implementation State: Fitted
Target Device: xc9572xl-5VQ44
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 14 09:00:14 2016000
Translation ReportCurrentWed Dec 14 09:00:18 2016000
CPLD Fitter Report (Text)CurrentWed Dec 14 09:00:20 201602 Warnings (1 new)1 Info (1 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 06/28/2018 - 14:53:57