logic Project Status | |||
Project File: | OwlPress.xise | Parser Errors: | No Errors |
Module Name: | logic | Implementation State: | Fitted |
Target Device: | xc9572xl-5VQ44 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Dec 14 09:00:14 2016 | 0 | 0 | 0 | |
Translation Report | Current | Wed Dec 14 09:00:18 2016 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | Wed Dec 14 09:00:20 2016 | 0 | 2 Warnings (1 new) | 1 Info (1 new) | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Fit Simulation Model Report |