- Dr Jose Miguel Montanana Aliaga (2015-2016, EU FP7 DreamCloud Project)
- Dr Amit Kumar Singh (2014-2016, EU FP7 DreamCloud Project)
- Dr Piotr Dziurzanski (2014-2015, EU FP7 DreamCloud Project)
- Dr Andrew Burkimsher (2014-2015, EU FP7 DreamCloud Project)
Full doctoral genealogy at the Mathematics Genealogy Project.
Feel free to email me about any of the topics below. Last update: Oct 2016.
Application-specific multiprocessor, high-performance and cloud computing
The mapping of application tasks onto computing platforms has critical impact over the performance and energy-efficiency of computer systems, as the mapping process partitions the application and allocates the platform resources that will execute each of the partitions. This problem has been addressed since the dawn of computing, but its importance has grown recently because of the additional complexity imposed by the potential availability of massive parallelism at the platform level. Many of the existing heuristics can still be used for finding initial mappings, but the dynamic nature of complex systems requires the mapping to be re-done during runtime in order to adapt to the new situation. To cope with such cases, new heuristics must be found so that their impact is minimal regarding (a) the information they need about the platform state, (b) the overhead caused by the re-mapping of the different parts of an application, and (c) the execution overhead of the heuristic itself.
Possible PhD topics:
- Evolutionary algorithms have been currently used to statically optimise design and mapping of multiprocessor platforms. Timeliness and energy dissipation have been comprehensively addressed, but there is still scope for a further research on optimising other relevant aspects to multicore embedded systems such as reliability and security, or on coping with the issues raised by the latest semiconductor advances, such as variability and silicon aging.
As the computational power of such platforms keeps increasing, and so does the complexity and dynamism of applications they execute, it is natural to assume that evolutionary algorithms could also be employed during runtime to "evolve" optimised configurations and mappings as the dynamics of the system changes. Interesting research questions include the fine-tuning of the evolutionary approach (which could be done statically or also during runtime) and the decision on how much of the platform resources should be allocated to the evolutionary algorithm itself (how many cores, how much of the interconnect, how to bound its utilisation) so that its overhead will always be less than the optimisation benefits it provides.
M.N.S.M. Sayuti and L.S. Indrusiak, Real-time low-power task mapping in Networks-on-Chip, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013.
M.N.S.M. Sayuti and L.S. Indrusiak, A Function for Hard Real-Time System Search-Based Task Mapping Optimisation, in: IEEE Int Symposium on Real-Time Distributed Computing (ISORC), 2015.
- Pheromone signalling is a decentralised load balancing algorithm created by Ipek Caliskanelli and myself, inspired on the behaviour of queen bees, and originally applied to wireless sensor networks. It is general enough to be used in many kinds of distributed and multiprocessor systems, and could be adapted to solve problems such as fault tolerance, resource allocation and duplication management.
I. Caliskanelli et al, Bioinspired Load Balancing in Large-Scale WSNs Using Pheromone Signalling, International Journal of Distributed Sensor Networks, 2013.
H. R. Mendis et al, Bio-inspired distributed task remapping for multiple video stream decoding on homogeneous NoCs, in: ESTImedia, 2015.
- Cloud resource management is a key challenge to achieve performance predictability and energy efficient in large scale cloud systems. Our market-inspired techniques have shown promising results by unifying performance, time and energy under the notion of value, providing a simple and yet powerful metric to guide allocation heuristics.
A.K. Singh, P. Dziurzanski, L. S. Indrusiak, Market-inspired dynamic resource allocation in many-core high performance computing systems, in: HPCS, 2015.
A.K. Singh, P. Dziurzanski, L. S. Indrusiak, Value and Energy Optimizing Dynamic Resource Allocation in Many-Core HPC Systems, in: CloudCom, 2015.
Multiprocessor platforms for embedded systems
Chips with multiple processing cores are already a reality in embedded systems, but there are many open issues on how to maximize system performance through parallelism while complying with constraints on chip area, cost, power consumption and heat dissipation. In order to find the best trade-off for each embedded application, developers must be able to validate the software functionality and performance over different alternatives of the hardware platform, and due to short time-to-market this is expected to be done even before the actual hardware is available.
Possible PhD topics:
- Mixed-criticality many-core systems and interconnects, which are needed to provide performance guarantees that are custom-tailored to systems that perform computation at different levels of criticality: from safety-critical to mission-critical to best-effort.
A. Burns, J. Harbin and L. S. Indrusiak, A Wormhole NoC Protocol for Mixed Criticality Systems, in: Real-Time Systems Symposium (RTSS), 2014.
L. S. Indrusiak, J. Harbin and A. Burns, Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip, in: EUROMICRO Conference on Real-Time Systems (ECRTS), 2015.
- Design and evaluation of time-predictable network-on-chip interconnects, aiming to provide the software and OS layers with timing guarantees on multi-processor communication latency. Special attention must be given to the different types of guarantees that must be provided at each step of the design flow (from early specification to cycle-accurate models), and how the guarantees from one step can be extended so that they also hold at lower abstraction levels. Architectural features to be explored here include networks-on-chip with different flow control mechanisms (circuit switching, wormhole switching, virtual channels).
L. S. Indrusiak, J. Harbin and O. M. dos Santos, Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration, ACM Transactions on Design Automation of Electronic Systems (TODAES), 20(4), 2015.
- Evolutionary algorithms are highly parallelisable and have well defined communication patterns, so it is likely that specific optimisations on the memory hierarchy and on-chip interconnects of multiprocessor platforms could be proposed aiming to accelerate the execution of such algorithms. A relevant research question is to identify different types of evolutionary algorithms (regarding their mutation, crossover and selection methods) and evaluate which kind of architectural optimisation would benefit each of them.
Y. Ma and L. S. Indrusiak, Hardware-Accelerated Parallel Genetic Algorithm for Fitness Functions with Variable Execution Times, in: Genetic and Evolutionary Computation Conference (GECCO), 2016.
Y. Xue et al, An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms, in: IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2014.
- Security in Network-on-Chip interconnects is a novel area of research, aiming to devise mechanisms that can make it harder for an attacker to obtain sensitive information by monitoring the behaviour of the NoC interconnect. The monitoring can be done by malicious applications using the NoC, or even by an external attacker using covert channels (e.g. temperature or electromagnetic activity). An important research question is to identify mechanisms that can improve NoC security without jeopardising performance guarantees, specially in the case of hard real-time applications.
L. S. Indrusiak, J. Harbin, and M. J. Sepulveda, Side-Channel Attack Resilience through Route Randomisation in Secure Real-Time Networks-on-Chip, arXiv:1607.03450 [cs.DC], 2016.
M. J. Sepulveda, J.-P. Diguet, M. Strum, and G. Gogniat, NoC-Based Protection for SoC Time-Driven Attacks, IEEE Embedded Systems Letters, vol. 7, no. 1, pp. 7-10, Mar. 2015.
Y. Wang and G. E. Suh, Efficient Timing Channel Protection for On-Chip Networks, in: Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, Washington, DC, USA, 2012, pp. 142-151.
- Mobile and autonomous robotic systems are based on a number of inter-related control loops. The communication flows between sensors, controllers and actuators have timing requirements with different degrees of strictness. There are many open issues on the use of on-chip multiprocessing to handle such control loops within a single-chip solution. We have prototyping platforms based on quadcopters and autonomous four-wheel vehicles, using high definition cameras and LIDARs to sense the environment, and would like to evaluate different on-chip multiprocessor architectures through FPGA boards integrated to those prototypes.
Model-driven Design of IoT Systems (Internet of Things)
An important aspect of developing any system is having an appropriate way for describing both the problem and solution domains. This is particularly critical when designing IoT systems, because they are applied to different domains such as industrial process monitoring or shopper's behaviour prediction. Specialists in those areas know their problem quite well but are not necessarily willing to learn details about IoT technology challenges and issues. My model-based approach to IoT is based on a complete separation of concerns: one model which describes a distributed sensing and actuation application (possibly specified by a problem domain specialist) and a set of models which describe possible IoT platforms and protocols that are supposed to provide the resources for the application's execution. The research questions that arise from such a paradigm include the definition of domain-specific modelling languages, application-platform mapping, design space exploration and platform validation.
Possible PhD topics:
- Domain-specific modelling of distributed sensing and actuation applications involves the definition of a system specification language that can be adapted/extended to different application domains (in such a way that domain specialists would feel comfortable using it) while at the same time providing unambiguous description of the system requirements (in such a way it can be used to automatically generate fitness functions to evaluate alternative implementation platforms)? There's a continuum of possibilities to choose from when designing such language. In one extreme, language constructs are closely related to one application domain and which use models of time, concurrency and idleness that match the domain experts' basic notions. On another, the languages that provide little abstraction of the IoT components (e.g. Mote Runner). The goal here is to investigate a language that can support (most of) domain specialist's notions and produces models that allow successive transformation towards implementation-related notions so that increasingly accurate performance and power consumption figures can be obtained.
L. Brisolara, P. R. Ferreira, and L. S. Indrusiak, Application modeling for performance evaluation on event-triggered wireless sensor networks, in: Design Autom. for Emb. Sys., 20(4), 2016. p. 269-287.
- Optimisation for domain-specific IoT deployments is a crucial process to search for system configurations that suit application-specific constraints. This process includes heuristics to generate different configurations, which can be based on different topologies, protocols, organisation, node storage and computation capacities, etc. Because of the multiple alternatives, the resulting design space is vast and multidimensional, so efficient search heuristics are necessary and fast fitness functions must be devised to quickly rule out unsuitable configurations.
I. Caliskanelli, and L. S. Indrusiak, Search-Based Parameter Tuning on Application-Level Load Balancing for Distributed Embedded Systems, in: IEEE International Conference on Embedded and Ubiquitous Computing (EUC), 2013.
- Adaptive behaviour in IoT can be achieved by orchestrating the way each individual node reacts to changes in the application's goals, the environment or in the nodes themselves. Our approach to adaptive behaviour is to allow each node to decide which services it provides to the network, taking into account the application objectives, its perceived state of the network and its own state. The application objectives include the end-user goals with the IoT deployment, which are known a priori but could change after deployment. The state of the network and the node can include the power budget of the node, information about reachable neighbors, services provided by them, etc. Based on that information, each node can choose which services it should provide to its neighbors and, ultimately, to the end user. Such decision can be very conservative, e.g. in case it power budget is limited, aiming to extend the lifetime of the network to the detriment of its performance. On the other hand, it may decide to provide a large set of services if its contribution is critical to the success of the system. In other words, a node becomes more "egoistic" and refuses to provide one (or more) of the services it is capable to provide if it "feels" that its own "existence" is threatened by lack of power, or more "altruistic" if it "feels" that the network depends heavily on it. The research goal here is to evaluate different ways to address such trade-off: when should a node restrict access to its services? how to know which of the services should be restricted first? how to handle the mobility of nodes? are there any "bio-inspired" methods that could be used to model the egoistic vs. altruistic behaviour of each particular node? can we use hardware reconfiguration as a way to dynamically enable nodes to provide services that are needed at a given point in time?
I. Caliskanelli et al, Bioinspired Load Balancing in Large-Scale WSNs Using Pheromone Signalling, International Journal of Distributed Sensor Networks, 2013.
P. R. Ferreira, L. Brisolara, and L. S. Indrusiak, Decentralised Load Balancing in Event-Triggered WSNs Based on Ant Colony Work Division, in: 41st EUROMICRO Conference on Software Engineering and Advanced Applications (SEAA), 2015.
(updated on 15.02.2017)
- Benchmarks for multi and many-core systems. 2016. M.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Anthony Williams
- Maker Culture and Home Automation - An Experimental Study Focused on Multi-Room Audio. 2016. B.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Alistair Blair
- Simulating Auction Style Resource Allocation in Cloud Computing. 2015. M.Sc. in Information Technology. University of York, UK.
Author: James Dipper
- Acoustic localisation in wireless sensor networks using Mote Runner. 2015. M.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Henri Normak
- Simulation of video processing algorithms using Ptolemy II. 2015. M.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Ross Brown
- Network-on-Chip Simulation Visualisation. 2015. M.Eng. in Computer Science. University of York, UK.
Author: Ashley Coombs
- Altruistic and egoistic behaviour in wireless sensor networks. 2014. M.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Andrew Faulkner
- Using Wireless Sensor Networks to Produce Music. 2014. M. Eng. Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Adam Fahie
- Simultaneous Localisation and Mapping for Mobile Robotics. 2014. M.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Anthony Free
- Simulating resource allocation mechanisms in Cloud Computing. 2013. M.Sc. in Information Technology. University of York, UK.
Author: Hanwen Zhang
- Heuristics for dynamic mapping of tasks in multicore systems. 2013. M.Eng. in Computer Systems and Software Engineering. University of York, UK.
Author: Steven Fisher
- Scheduling Topology Reconfiguration for Networks on Chips. 2013. B.Eng. in Computer Science with Embedded Systems Engineering. University of York, UK.
Author: Lyubomir Chernev
- Iterative linear programming as an optimisation method for buyer resources in online auctions evaluated using a Java-based Monte-Carlo simulation. 2012. M.Sc. in Information Technology. University of York, UK.
Author: Daniel Baark
- Mapping of Real-time Applications on Network-on-Chip based MPSoCs. 2012. M.Sc. by Research in Computer Science. University of York, UK.
Author: Paris Mesidis
- Static Scheduling of Tasks in Large Multicore Systems Using Evolutionary Computation Techniques. 2012. M.Eng. in Computer Systems and Software Engineering. University of York, UK.
Author: Adrian Racu
- Exploring Multi-Hop Communication in Wireless Sensor Networks using Mote Runner. 2012. M.Eng. in Computer Systems and Software Engineering. University of York, UK.
Author: Brian Wong
- A Web Interface for In-home Monitoring using Wireless Sensor Networks and Mote Runner. 2012. M.Eng. in Computer Systems and Software Engineering. University of York, UK.
Author: Mohammed Omar
- Applying pattern matching techniques to online penny auctions. 2012. B.Eng. in Computer Science. University of York, UK.
Author: Alastair Clark
- A web interface for wireless deployment of Mote Runner applications on sensor motes. 2012. B.Eng. in Computer Science. University of York, UK.
Author: Robert Cazaciuc
- Runtime Monitoring of Inter-task Communication in Multi-core Architectures. 2010. M.Sc. in Information Technology. University of York, UK.
Author: Okowa Aghudum
- Efficient request/response support in multicore architectures. 2010. M.Sc. in Information Technology. University of York, UK.
Author: Jianping Zhou
- Indoor Localization using fingerprinting technique in minimal wireless sensor network setup. 2010. M.Sc. in Computing. University of York, UK.
Author: Ujwal Bhagwat
- Static mapping of tasks in large multicore systems using evolutionary algorithms. 2010. M.Sc. in Computing. University of York, UK.
Author: Xiaojie Zhang
- Broadcast-based Geographical Information System: a feasibility study concerning map data partitioning. 2010. B.Eng. in Computer Science. University of York, UK.
Author: Derek Wicks
- Comparative Analysis of Object Oriented and Procedural Programming Methodologies on the Android Platform. 2009. M.Sc. in Information Technology. University of York, UK.
Author: Akshay Dashrath
- Design and implementation of a web-based database system to manage international academic collaboration activities. 2009. M.Sc. in Information Technology. University of York, UK.
Author: Shasha Du
- Service availability management in power-constrained ad-hoc networks. 2009. M.Sc. in Computing. University of York, UK.
Author: Tarun Chhabra
- Availability management of Composable Services for Wireless Sensor Networks. 2008. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Diego Alonso Ahogado Alvarez
- Design Space Exploration of the On-Chip Interconnect Structure of a Graphic Display Controller Using VisualSim. 2008. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Xi Liu
- TinyOS Extensions Supporting Abstract Behavioral Modeling based on a Type System. 2007. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Andreas Thuy
- VHDL Hardware Design and Implementation of a Camera-Link Framegrabber based on a Dynamic Reconfigurable Image Processing Kernel. 2007. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Cihan Senel
- Parallele Prozesse in rekonfigurierbaren Rechnersystemen: Entwurfsraumanalyse und Fallstudien. 2006. M.Sc. in Electrical Engineering. TU Darmstadt, Germany.
Author: Christopher Spies
- Programmability support in a LEON2-based wireless sensor network node. 2006. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Enkhbold Ochirsuren
- VHDL Hardware Entwurf und Implementierung dynamisch rekonfigurierbarer Module auf einer Virtex-4 FPGA. 2006. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Abdelmajid El Mahjoub
- Unterstützung paralleler Befehlausführung in rekonfigurierbarer Hardware durch die Verwendung codegenerierender Actor-Bibliotheken. 2006. M.Sc. in Electrical Engineering. TU Darmstadt, Germany.
Author: Florian Markert
- Exploring Concurrency at Instruction Level on Reconfigurable Computing Platforms. 2005. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Hua Zhong
- Real-time Operating System Support for LEON based Reconfigurable Hardware. 2005. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Muhammed Najmul Huda
- Actor-oriented Encapsulation of Reconfigurable Prototyping Platforms. 2005. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Diego Jimenez Orostegui
- VHDL Hardware-Entwurf und Implementierung modularer Algorithmen zur Farbrückgewinnung und Transformation eines CMOS Videosignals. 2005. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Stefan Zink
- VHDL-Entwurf und Implementierung eines parametrisierbaren Algorithmus zur Echtzeit-Binärisierung von Videodaten. 2005. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Adeel Ashraf
- VHDL Entwurf und Implementierung eines modularen Hardware-Bildverarbeitungsalgorithmus für Lichtschnittverfahren. 2004. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Friedhelm Mayer
- Analysis, Design and FPGA Implementation of a Reconfigurable Equalizer for WCDMA using Actor-oriented Modeling and Co-Simulation Tools. 2004. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Romualdo Begale Prudêncio.
- Analysis, Design and FPGA Implementation of Chaotic Systems as Alternative for Gaussian Noise Generation. 2004. M.Sc. in Information and Communication Engineering. TU Darmstadt, Germany.
Author: Elvio Carlos Dutra e Silva Jr.
- Typabstraktion für Jini-eingebettete rekonfigurierbare Hardware (Typing abstraction for Jini-encapsulated reconfigurable hardware). 2002. Diploma in Electrical Engineering. TU Darmstadt, Germany.
Author: Florian Lubitz